EI701 VLSI Design Syllabus
RGTU/RGPV VLSI Design Syllabus
Electronics and Instrumentation EI VII-7th Semester Syllabus
Unit-II
The complementary CMOS inverter-DC character, Static load MOS inverters. The differential inverter. Tristate inverter. Bipolar devices, diodes, transistors, BICMOS inverters.
Unit-III
Review of silicon semiconductor technology and basic CMOS technology-n-well and p-well process. Interconnect and circuit Twin-tub process layout design rules and latch-up, latch-up triggering and prevention.
Unit-IV
Circuit characterization and performance estimation resistance and capacitance estimation, Switching
characteristics, CMOS gate transistor sizing, power dissipation. Basic physical design of simple logic
gates. CMOS logic structure.
Unit-V
CMOS design methods. Design strategies. Programmable logic, programmable logic structure, reprogrammbale gate arrays. Exiling programmable gate array. Algotonix, concurrent logic, sea of gate and gate array design VHDL as a tool.
EI701 VLSI Design Course Contents:
Unit-I
Introduction to CMOS circuit, Circuit & System representation Behavioral representation, structural representation. Physical representation MOS transistor theory. NMOS and PMOS enhancement transistor. Threshold voltage, body effect. MOS device design equation. Basic DC equation, second order effects, MOS models.
Introduction to CMOS circuit, Circuit & System representation Behavioral representation, structural representation. Physical representation MOS transistor theory. NMOS and PMOS enhancement transistor. Threshold voltage, body effect. MOS device design equation. Basic DC equation, second order effects, MOS models.
Unit-II
The complementary CMOS inverter-DC character, Static load MOS inverters. The differential inverter. Tristate inverter. Bipolar devices, diodes, transistors, BICMOS inverters.
Unit-III
Review of silicon semiconductor technology and basic CMOS technology-n-well and p-well process. Interconnect and circuit Twin-tub process layout design rules and latch-up, latch-up triggering and prevention.
Unit-IV
Circuit characterization and performance estimation resistance and capacitance estimation, Switching
characteristics, CMOS gate transistor sizing, power dissipation. Basic physical design of simple logic
gates. CMOS logic structure.
Unit-V
CMOS design methods. Design strategies. Programmable logic, programmable logic structure, reprogrammbale gate arrays. Exiling programmable gate array. Algotonix, concurrent logic, sea of gate and gate array design VHDL as a tool.
References:
- Neil, H.E. Wasdte, Kamran Eshraghian, Principles of CMOS VLSI design, Pearson Education. Wyne Wolf, Modern VLSI Design-system on silicon, PHI.
- Phillip E. Allen and Douglas R holding, CMOS Analog Circuit Design, 2nd edition, Oxford University press.
List of Experiments
1. Introduction to Tanner Tool 13.0 and its various domains.
2. Design CMOS Inverter using S-edit and getting its transient response.
3. Design Universal gates and all other gates using S-edit and getting its transient esponse.
4. Obtain the DC- characteristics of CMOS Inverter using DC-analysis.
5. Design Symbol of CMOS Inverter and using instances of its getting transient response.
6. Design Symbol of Universal gates and using instances of them getting transient esponse.
7. Design a Half Adder and Full adder using instances.
8. Design a Transmission gate using PMOS & NMOS by instance calling.
9. Introduction to Tanner L-edit.
10. Design the Layout of NMOS and PMOS transistor.
11. Design the Layout of CMOS Inverter.
12. Design the Layout of Universal gates.
13. Introduction to Hardware Description Language (HDLs).
14. Design all universal gates and flip-flops using different coding styles of VHDL.
15. Design a serial to parallel shift register using VHDL and download on FPGA kit.
1. Introduction to Tanner Tool 13.0 and its various domains.
2. Design CMOS Inverter using S-edit and getting its transient response.
3. Design Universal gates and all other gates using S-edit and getting its transient esponse.
4. Obtain the DC- characteristics of CMOS Inverter using DC-analysis.
5. Design Symbol of CMOS Inverter and using instances of its getting transient response.
6. Design Symbol of Universal gates and using instances of them getting transient esponse.
7. Design a Half Adder and Full adder using instances.
8. Design a Transmission gate using PMOS & NMOS by instance calling.
9. Introduction to Tanner L-edit.
10. Design the Layout of NMOS and PMOS transistor.
11. Design the Layout of CMOS Inverter.
12. Design the Layout of Universal gates.
13. Introduction to Hardware Description Language (HDLs).
14. Design all universal gates and flip-flops using different coding styles of VHDL.
15. Design a serial to parallel shift register using VHDL and download on FPGA kit.
EI 7th (VII) Semester syllabus, VLSI Design Syllabus
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