RGPV / RGTU B.E. EC, 5th (V) Semester syllabus EC 506 Software Lab-II ,EL VERILOG, VHDL, ECTRONIC DESIGN AUTOMATION SOFTWARE Revised syllabus Electro
B.E. (EC) Electronics and Communication Engineering FOURTH IV SEMESTER
EC 506 Software Lab-II ,EL VERILOG, VHDL, ECTRONIC DESIGN AUTOMATION SOFTWARE
Revised Syllabus and Scheme of Examination Effective from July 2007
Introduction to EDA environment, eg. Microwind / Cadence / Sylvaco / Tanner silicon HiPer / Xilinx ISE 9i / any similar software / Any Freeware - EDA, its study and simulation/analysis/design of circuits. (The EDA tool package should have equal number of perpetual licenses for all modules and should have GUI)
SECTION B: VERILOG
Introduction, Language Element, Expression, Gate Level Modeling, User-Defined Primitives, Data Flow Modeling, Behavioral Modeling, Structural Modeling, Synthesize, Verilog Constructs To G ate, Modeling- Combinational Logic, Modeling-Sequential Logic, Modeling A Memory.
SECTION C: VHDL
Introduction, Entity Declaration, Architecture Body, Configuration and Package Declaration, Package Body, Model Analysis, Simulation, Basic Language Elements, Behavioral Modeling, Data Flow Modeling, Structural Modeling.
1. J. Bhasker: A Verilog HDL Primer, New Edition, Pearson Education.
2. J. Bhasker: A Verilog HDL Synthesis, BS Publication.
3. D. L. Perry: VHDL: Programming by Example, TMH.
4. V. A. Pedroni: Circuit Design with VHDL, PHI.
5. J. R. Armstrong and F. G. Gray: VHDL Design Representation and Synthesis, Pearson Education.
6. Palnitkar: VHDL, Pearson Education.
7. Software Manuals.
List of Experiments:
Section A: Study and Experiments based on EDA environment.
Section B and C:Simulation of Following Using Verilog/VHDL.
1. Half Adder, Full Adder, Subtractor, Flip-Flop’s, 4-bit Comparators
2. Multiplexers - 2:1, 4:1 and 8:1
3. Parity Generator.
4. 4 Bit Up/Down Counter with Loadable Count.
5. Decoders –
6. 2:4, 3:8 and 4:16.
7. 8-bit Shift Resistors.
8. Barauel Shifter.
9. Design of 8-bit Arithmetic unit.
10. N by M Binary Multiplier.