EI - 303 Digital Circuits and Systems EI 3rd (Third) sem Electronics and Instrumentation(EI) Syllabus
Number systems & codes, Binary arithmetic, Boolean algebra and switching function. Minimization of switching function, Concept of prime implicant, Karnaugh map method, Quine & McCluskey's method, Cases with don't care terms, Multiple output switching function.
Introduction to logic gates, Universal gate, Half adder, Half subtractor, Full adder, Full subtractor circuits, Series & parallel addition, BCD adders, Look-ahead carry generator.
Linear wave shaping circuits, Bistable, Monostable & Astable multivibrator, Schmitt trigger circuits & Schmitt-Nand gates. Logic families: RTL, DTL, All types of TTL circuits, ECL, I2L, PMOS, NMOS & CMOS logic, Gated flip-flops and gated multivibrator, Interfacing between TTL to MOS.
Decoders, Encoders, Multiplexers, Demultiplexers, Introduction to various semiconductor memories & designing with ROM and PLA. Introduction to Shift Registers, Counters, Synchronous & asynchronous counters, Designing of Combinational circuits like code converters.
Introduction of Analog to Digital & Digital to Analog converters, sample & hold circuits and V-F converters.
1. M. Mano; "Digital Logic & Computer Design"; PHI.
2. Malvino & Leach; "Digital Principles & Applications”; TMH
3. W.H. Gothman; "Digital Electronics"; (PHI).
4. Millman & Taub; "Pulse, Digital & Switching Waveforms".(McGraw Hill)
5. R.J. Tocci, "Digital Systems Principles & Applications".
List of experiment (Expandable):
All experiments (wherever applicable) should be performed through the following steps.
simulated using Simulation S/W (TINA-V7/ PSPICE/ Labview/ CIRCUIT MAKER).
1. To study and test of operation of all logic gates for various IC’s (IC#7400,IC#7403,IC# 7408,IC#74332,IC#7486).
2. Verification of Demorgan’s theorem.
3. To construct of half adder and full adder
4. To construct of half subtractor and full subtractor circuits
5. Verification of versatility of NAND gate.
6. Verification of versatility of NOR gate.
7. Designing and verification of property of full adder.
8. Design a BCD to excess-3 code converter.
9. Design a Multiplexer/ Demultiplexer.