RGPV / RGTU B.E. EC, 5th (V) Semester syllabus EC 505 CMOS VLSI Design Revised syllabus Electronics and Communication Engineering (EC)

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Rajiv Gandhi Technological University, Bhopal (MP)
B.E. (EC) Electronics and Communication Engineering FOURTH IV SEMESTER
EC 505 CMOS VLSI Design
Revised Syllabus and Scheme of Examination Effective from July 2007

Unit -I Introduction
CMOS Logic: Inverter, NAND Gate, Combinational Logic, NOR Gate, Compound Gates, Pass Transistors and Transmission Gates, Tristates, Multiplexers, Latches and Flip-Flops, CMOS Fabrication and Layout: Inverter Crosssection, Fabrication Process, Layout Design rules, Gate Layout, Stick Diagrams. VLSI Design Flow.
MOS Transistor Theory: Ideal I-V Characteristics, C-V Characteristics: MOS Capacitance Models, MOS Gate Capacitance Model, MOS Diffusion Capacitance Model.
Non ideal I-V Effects: Velocity Saturation and Mobility Degradation, Channel Length Modulation, Body Effect, Subthreshold Conduction, Junction Leakage, Tunneling, Temp. and Geometry Dependence. DC Transfer characteristics: Complementary CMOS Inverter DC Characteristics, Beta Ratio Effects, Noise Margin, Ratioed Inverter Transfer Function, Pass Transistor DC Characteristics, Tristate Inverter, Switch- Level RC Delay Models.

Unit -II CMOS Processing Technology
CMOS Technologies: Background, Wafer Formation, Photolithography, Well and Channel Formation, Silicon Dioxide (SiO2), Isolation, Gate Oxide, Gate and Source/Drain Formation, Contacts and Metallization, Passivation, Metrology.
Layout Design Rules: Design Rules Background, Scribe Line and Other Structures, MOSIS Scalable CMOS Design Rules, Micron Design Rules.
CMOS Process Enhancements: Transistors, Interconnect, Circuit Elements, Beyond Conventional CMOS.

Unit -III Circuit Characterization and Performance Estimation
Delay Estimation: RC Delay Models, Linear Delay Model, Logical Effort, Parasitic Delay. Logical Effort and Transistor
Sizing: Delay in a Logic Gate, Delay in Multistage Logic Networks, choosing the Best Number of Stages.
Power Dissipation: Static Dissipation, Dynamic Dissipation, Low-Power Design.
Interconnect: Resistance, Capacitance, Delay, Crosstalk. Design Margin: Supply Voltage, Temperature, Process Variation, Design Corners. Reliability, Scaling.

Unit -IV Analog Circuits
MOS Small-signal Model, Common Source Amplifier, The CMOS Inverter as an Amplifier, Current Mirrors, Differential Pairs, Simple CMOS Operational Amplifier, Digital to Analog Converters, Analog to Digital Converters, RF Circuits.

Unit -V Combinational Circuit Design
Circuit Families: Static CMOS, Ratioed Circuits, Cascode Voltage Switch Logic, Dynamic Circuits, Differential Circuits, Sense Amplifier Circuits, BiCMOS Circuits, Low Power Logic Design, Comparison of Circuit Families.
Standard Cell Design: Cell Hierarchies, Cell Libraries, Library Entries, Cell Shapes and Floor Planning.

References:
1. Neil H.E. Weste, David Harris, Ayan Banerjee: CMOS VLSI Design, Third Edition, Pearson Education.
2. Neil H.E. Weste, Kamran Eshraghian: Principle of CMOS VLSI Design, Pearson Education.
3. J. P. Uyemura: Chip Design for Submicron VLSI, Cengage Learning.
4. Philip E. Allen and Douglas R Holberg: CMOS Analog Circuit Design, Oxford
5. Carver Mead and Lynn Conway: Introduction to VLSI systems, BS Publication.
6. J. P. Uyemura: Introduction to VLSI Circuits and Systems, Wiley.
7. Plummer: Silicon VLSI Technology, Pearson Education.

List of Experiments:
1. Design of MOS Generator Using any Electronic Design Automation (EDA)- eg. Microwind / Cadence / Sylvaco / Tanner silicon HiPer / Xilinx ISE 9i or any similar software
2. DC MOSFET Curves using EDA.
3. Design of CMOS Logic Gates using EDA.
4. Draw the following CMOS circuits using 0.12 μm and 65 nm technology and simulate for transfer characteristics along with 2D and 3D view from 450 angles. Compare power consumption and rise/fall delays in both technologies:
a. CMOS Inverter with 0.1pF and 0.1fF capacitance loads, in both cases with equal rise and fall times. Plot output eye diagram also.
b. CMOS NAND and NOR gates with 0.01pF load and equal rise and fall times. Comment on area
requirement of both gates.
5. To design Current Mirror using CMOS 0.18 micron Technology.
6. Design a basic differential amplifier circuit using current mirror logic. Show gain of amplifier and comment on bandwidth.
7. Design the Schmitt trigger circuit with UTP= 4.5 V and LTP = 2.0 V. Plot transfer curve analysis (with hysteresis effect) VO versus VI.
8. Design a 2-bit parallel adder from schematic and its CMOS layout. List global delay of all nodes. Identify the critical path and comment on its optimization.

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